1/4 rev. a structure silicon monolithic integrated circuit name of product led driver control ic type ? feature ? using 20v high-voltage-withstand process ? 1channel push-pull control ? current and voltage feedback is controlled by drive frequency modulation ? built-in soft start circuit ? built-in timer latch circuit ? built-in shut down protection ? built-in uvlo detection circuit ? output over voltage protection ? built-in error signal output function ? switching to current consumption save mode through stb pin ? possible to control the burst by external pwm absolute maximum ratings (ta=25 ) item symbol rated voltage unit power supply voltage vcc 20 v driver output n1,n2 20 v operating temperature topr -40 +85 storage temperature range tstg -55 +150 maximum junction temperature tjmax +150 power dissipation pd 687* mw * it reduces gradually by 5.5 mw/ if above ta= 25 (when mounting the board of 70.0mm70.0mm1.6mm) recommended operation ranges item symbol range unit power supply vcc 8.0 18.0 v pwmin input frequency range f_pwmin 60 500 hz output frequency fout 25 200 khz
2/4 rev. a electrical characteristics (vcc=12v, ta=25 ) parameter symbol limits unit conditions min. typ. max. whole device circuit current during operation icc1 2.3 5.0 ma fout=60khz, pwmcmp=gnd circuit current during stand by operation icc2 0 20 a vstb=0v stand by control stand-by voltage h vstbh 2.0 vcc v system stand-by voltage l vstbl -0.3 0.8 v system vcc uvlo block operating voltage (vcc) v_vccuvp 6.17 6.50 6.83 v hesteresis width (vcc uvlo) S v_vccuvp 0.37 0.50 0.63 v osc block rt output voltage vrt 1.05 1.50 1.95 v rt=79 k ? pwmin block pwmin pin h level input voltage range vpwminh 2.0 - 5.0 v pwmin pin l level input voltage range vpwminl 0.3 - 0.8 v soft start block set up current for soft start iss 1.5 2.0 2.5 ua soft start end voltage vss_end 2.8 3.0 3.2 v feed back block is threshold voltage vis 1.225 1.250 1.275 v vs threshold voltage vvs 1.212 1.250 1.288 v is source current 1 iis1 0.9 a pwmin=2.5v is source current 2 iis2 40 50 60 a pwmin=0v, is=1.0v vs source current ivs 0.9 a is comp detect voltage viscomp 0.606 0.625 0.644 v output block n1 output sink resistance rsink_n1 1.5 3.0 6.0 ? n1 output source resistance rsource_n1 4.5 9.0 18.0 ? n2 output sink resistance rsink_n2 1.5 3.0 6.0 ? n2 output source resistance rsource_n2 4.5 9.0 18.0 ? max duty max duty 43.0 45.0 47.0 % fout=60khz n1-n2, n2-n1 off period toff 100 200 400 ns drive output frequency fout 57.9 60.0 62.1 khz rt=79 k ? timer latch block cp timer latch detect voltage vcp 1.90 2.00 2.10 v cp timer latch charge current icp 0.85 1.00 1.15 a sdon latch detect voltage vsdon 1.90 2.00 2.10 v sdon latch charge current isdon 0.85 1.00 1.15 a comp block comp over voltage detect voltage vcomp 3.88 4.00 4.12 v hysteresis width comp S vcomp 0.15 0.20 0.25 v compsd over voltage detect voltage vcompsd 3.88 4.00 4.12 v fail block fail on resistor value rfaill - 100 200 ? this product is not designed to be radiation-resistant.
3/4 rev. a external dimensions , marking block diagram pin number, pin name, pin function pin no pin name functions pin no pin name functions 1 vcc power supply pin for ic built-in uvlo function 10 pwmin pwm signal input pin for burst bright adjustment control 2 stb power on/off control pin for ic 11 sdon enable pin of compsd inputs over voltage detection 3 gnd signal/ground pin for internal ic 12 ss soft-start set up pin 4 rt drive frequency set up terminal. 13 fail error indication signal output normal : l, error : open 5 fb lamp current, lamp voltage, error amp outputs 14 compsd detection pin for over voltage shut down 6 is error amp input pin for lamp current feedback 15 comp detection pin for over voltage and shut-down delay 7 vs error amp input pin for lamp voltage feedback at the opening time. 16 pgnd power ground for external mosfet drive 8 pwmcmp pwm comparator input pin which controls pwm operation during brightness adjustment. 17 n2 output pin for external fet drive circuit (ch. n2) 9 cp timer latch-setting pin 18 n1 output pin for external fet drive circuit (ch. n1) BD9211F lot no. dvice mark sop18 (unit:mm)
4/4 rev. a note for use . when designing the external circ uit, including adequate margins for variation betwe en external devices and ic. use adequate mar gins for steady state and transient characteristics. . the circuit functionality is guaranteed within of ambient tem perature operation range as long as it is within recommended opera ting range. the standard electrical characterist ic values cannot be guaranteed at other voltages in the operating ranges, however th e variation will be small. . mounting failures, such as misdirecti on or miscounts, may harm the device. . a strong electromagnetic field may cause the ic to malfunction. . the gnd pin should be the location within 0.3v compared with the pgnd pin. . if the voltage between vcc and i/o pins or gnd and i/o pins is in opposite from the normal potential difference, unusual curren t flow into pins may occur which can destroy the ic. to avoid such occurrence it is recommended to pl ace protection diodes for prevent ion against backward current flow. . BD9211F incorporate a built-in thermal shutdown circuit (tsd circ uit). the thermal shutdown circ uit (tsd circuit) is designed o nly to shut the ic off to prevent runaway thermal operation. it is not designed to protect the ic or guarantee its operation of the th ermal shutdown circuit is assumed. . absolute maximum ratings are those values that, if exceeded, ma y cause the life of a device to become significantly shortened. moreover, the exact failure mode c aused by short or open is not defined. physical countermeasures, such as a fuse, need to be considered when using a device beyond its maximum ratings. . about the external fet, the parasitic capa citor may cause the gate voltage to change, when the drain voltage is switching. make sure to leave adequate margin for this ic variation. . by stb voltage, BD9211F are changed to 2 states. therefore, do not input stb pin voltage between one state and the other state (0.8 2.0v). . the pin connected a connector need to connect to the resistor for electrical surge destruction. this ic is a monolithic ic which (as shown is fig.4)has p + substrate and between the various pins . a p-n junction is formed from this p layer of each pin. for example, t he relation between each potential is as follows, (when gnd > pinb and gnd > pina, the p-n junction operates as a parasitic diode.) (when pinb > gnd > pina, the p-n junction operates as a parasitic transistor.) parasitic diodes can occur inevitably in the structure of the ic . the operation of parasitic diodes can result in mutual interf erence among circuits as well as operation faults and physical damage. acco rdingly you must not use methods by which parasitic diodes operate, such as applying a voltage that is lower than the gnd (p substrate) voltage to an input pin fig.4. simplified struct ure of a bipolar ic other adjacent components parasitic diode (pinb) parasitic (pina) parasitic diode resistance p substrate (pina) transistor (npn) parasitic diode p substrate (pinb)
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